Memory device with multi-layer channel and charge trapping layer
US10020317B2 · kind B2 · utility
6Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Mar 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.