Lei Xue
84Patents
4h-index
168Co-inventors
65Inventor score
Filing activity: Aug 2, 2005 → Dec 8, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7416940B1 | Methods for fabricating flash memory devices | Electricity | 9 | Active |
| US7053445B1 | Memory device with barrier layer | Electricity | 7 | Expired |
| US8652907B2 | Integrating transistors with different poly-silicon heights on the same die | Electricity | 6 | Active |
| US10020317B2 | Memory device with multi-layer channel and charge trapping layer | Electricity | 6 | Active |
| US8598005B2 | Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices | Electricity | 4 | Active |
| US8143661B2 | Memory cell system with charge trap | Electricity | 4 | Active |
| US8866213B2 | Non-Volatile memory with silicided bit line contacts | Electricity | 4 | Active |
| US9437470B2 | Self-aligned trench isolation in integrated circuits | Electricity | 3 | Active |
| US9252154B2 | Non-volatile memory with silicided bit line contacts | Electricity | 3 | Active |
| US11094714B2 | Three-dimensional memory devices and fabricating methods thereof | Electricity | 3 | Active |
| US9734074B2 | Data copy avoidance across a storage | Physics | 2 | Active |
| US11302627B1 | On-chip capacitors in three-dimensional semiconductor devices and methods for forming the same | Electricity | 2 | Active |
| US7951675B2 | SI trench between bitline HDP for BVDSS improvement | Electricity | 2 | Active |
| US8809206B2 | Patterned dummy wafers loading in batch type CVD | Electricity | 2 | Active |
| US8279674B2 | High read speed memory with gate isolation | Electricity | 2 | Active |
| US11563021B2 | Memory device and method for forming the same | Electricity | 2 | Active |
| US9589805B2 | Split-gate semiconductor device with L-shaped gate | Electricity | 2 | Active |
| US11348936B2 | Three-dimensional memory devices and fabricating methods thereof | Electricity | 2 | Active |
| US9831114B1 | Self-aligned trench isolation in integrated circuits | Electricity | 1 | Active |
| US10193910B2 | Network attack detection method | Electricity | 1 | Active |
| US11215543B1 | Rock mass shear test system for high-energy accelerator computed tomography (CT) scanning | Physics | 1 | Active |
| US10879263B2 | Three-dimensional memory devices with architecture of increased number of bit lines | Physics | 1 | Active |
| US11287356B1 | Variable angle loading testing machine | Physics | 1 | Active |
| US9252026B2 | Buried trench isolation in integrated circuits | Electricity | 0 | Active |
| US11314910B1 | Discrete element method-based simulation method and system for acoustic emission | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.