Resistive memory device by substrate reduction
US10020346B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 2016 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | May 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.