Memory cell and manufacturing method thereof
US10020385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2014 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Mar 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/696
Abstract
The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.