Semiconductor device and semiconductor device manufacturing method
US10020390B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Jul 10, 2018 |
| Priority date | — |
| Expiry date | Aug 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D12/031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.