Semiconductor device having network-on-chip structure and routing method thereof
US10025506B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Mar 24, 2015 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Apr 9, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of semiconductor chips vertically stacked and electrically coupled to one another through TSVs (Through-Silicon Vias), a plurality of semiconductor elements formed in each of the semiconductor chips, a plurality of nodes suitable for coupling the semiconductor elements to one another, and a node control device suitable for being provided in each of the nodes, deciding whether to couple the node to a communication path based on a temperature of the node, and setting a shortest communication path among the semiconductor elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.