Memory interface command queue throttling
US10025522B2 · kind B2 · utility
11Cited by
0References
16Claims
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Assignee
Inventor
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Apr 22, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device with a memory may implement command throttling in order to control power usage. The throttling may be based on modifications of certain memory parameters, such as a reduction in clock rate, bus speed, operating voltage, or command type changes. The throttling may be performed at a back end or memory interface of the storage device such that the memory interface receives un-throttled commands and can optimally throttle all of the commands from the front end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.