Adaptive hard and soft bit decoding
US10025661B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2016 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Dec 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.