Supporting multi-level nesting of command buffers in graphics command streams at computing devices
US10026142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2015 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Sep 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is described for facilitating multi-level nesting of batch buffers at computing devices. A method of embodiments, as described herein, includes facilitating a hardware extension to accommodate a plurality of batch buffers to engage in a multi-level nesting, where the plurality of batch buffers are associated with a graphics processor of a computing device. The method may further include facilitating the multi-level nesting of the plurality of batch buffers, where the multi-level nesting is spread over a plurality of levels associated with the plurality of batch buffers, where the plurality of levels include more than two levels of nesting associated with more than two batch buffers of the plurality of batch buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.