Semiconductor device for testing large number of devices and composing method and test method thereof
US10026661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Sep 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.