Stacked die package with aligned active and passive through-silicon vias
US10026666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2014 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Nov 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.