Integrated circuit chip and integrated circuit wafer with guard ring
US10026699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2017 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Feb 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04941
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.