Semiconductor package and method of manufacturing the same
US10026724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2017 |
| Grant date | Jul 17, 2018 |
| Priority date | — |
| Expiry date | Feb 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.