Integrated circuit package receiving test pattern and corresponding signature pattern
US10031181B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jun 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure include an integrated circuit (IC) that includes a first input port configured to receive a test pattern, a second input port configured to receive a signature pattern, a set of interconnected circuit elements, and a comparison circuit. The signature pattern is indicative of an expected test output pattern in response to the test pattern. The set of interconnected circuit elements is configured to generate a test output pattern in response to the test pattern being passed through the set of interconnected circuit elements. The comparison circuit is configured to compare the test output pattern to the signature pattern, generate a test result based on a comparison result of the test output pattern to the signature pattern, and output the test result to the test apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.