Inventor · Sachnin, IL

Yosef Solt

24Patents
7h-index
16Co-inventors
66Inventor score

Filing activity: Jan 11, 1996 → Jun 17, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US7539915B1 Integrated circuit testing using segmented scan chains Physics 22 Expired
US7206988B1 Error-correction memory architecture for testing production errors Physics 14 Expired
US5790891A Synchronizing unit having two registers serially connected to one clocked elements and a latch unit for alternately activating the registers in accordance to clock signals Physics 12 Expired
US8208326B1 Method and apparatus for memory test Physics 12 Active
US6988237B1 Error-correction memory architecture for testing production errors Physics 10 Expired
US7949908B2 Memory repair system and method Physics 9 Active
US6829245B1 Head of line blocking Electricity 9 Expired
US8423839B2 Memory repair system and method Physics 7 Active
US8176388B1 System and method for soft error scrubbing Physics 4 Active
US7689793B1 Buffer management architecture Physics 4 Active
US9726722B1 Systems and methods for automatic test pattern generation for integrated circuit technologies Physics 3 Active
US8572412B1 Method and apparatus for warming up integrated circuits Physics 3 Active
US8829898B1 Method and apparatus for testing Physics 2 Active
US8615688B2 Method and system for iteratively testing and repairing an array of memory cells Physics 2 Active
US8661223B1 Buffer management architecture Physics 2 Active
US9093127B1 Method and apparatus for warming up integrated circuits Physics 2 Active
US7886207B1 Integrated circuit testing using segmented scan chains Physics 1 Active
US7478308B1 Error-correction memory architecture for testing production Physics 1 Active
US10031181B1 Integrated circuit package receiving test pattern and corresponding signature pattern Physics 1 Active
US8176291B1 Buffer management architecture Physics 1 Active
US7730341B1 System and method for transitioning from a logical state to any other logical state by modifying a single state element Electricity 1 Active
US8526255B1 Method and apparatus for memory test Physics 0 Active
US8051348B1 Integrated circuit testing using segmented scan chains Physics 0 Active
US7984358B1 Error-correction memory architecture for testing production errors Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.