Patent · US Active

Cached memory structure and operation

US10031869B1 · kind B1 · utility

1Cited by

2References

20Claims

0Family size

Assignee

Adesto Technologies Corporation · US

Inventors

Gideon Intrater · Sunnyvale, US
Bard Pedersen · Fremont, US
Paul Hill · Eastleigh, GB

Key dates

Filing date	Mar 23, 2015
Grant date	Jul 24, 2018
Priority date	—
Expiry date	May 7, 2035

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.