Integrated circuit performance modeling using a connectivity-based condensed resistance model for a conductive structure in an integrated circuit
US10031989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2014 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jul 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.