Techniques for maintaining atomicity and ordering for pixel shader operations
US10032245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2015 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | May 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.