Sense amplifier layout for FinFET technology
US10032490B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Oct 10, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Oct 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.