Kao-Cheng Lin
43Patents
5h-index
43Co-inventors
65Inventor score
Filing activity: Oct 22, 2008 → Jul 31, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9208858B1 | Static random access memory with assist circuit | Physics | 67 | Active |
| US9129707B2 | Dual port SRAM with dummy read recovery | Physics | 20 | Active |
| US10650882B2 | Static random access memory with a supplementary driver circuit and method of controlling the same | Physics | 13 | Active |
| US9257172B2 | Multi-port memory cell | Physics | 12 | Active |
| US9412742B2 | Layout design for manufacturing a memory cell | Electricity | 6 | Active |
| US9275710B2 | Three dimensional cross-access dual-port bit cell design | Physics | 4 | Active |
| US9093126B2 | Memory circuit | Physics | 4 | Active |
| US9524920B2 | Apparatus and method of three dimensional conductive lines | Electricity | 3 | Active |
| US7800111B2 | Trench silicon-on-insulator (SOI) DRAM cell | Electricity | 2 | Active |
| US9466493B2 | Sense amplifier layout for FinFET technology | Electricity | 2 | Active |
| US9685224B2 | Memory with bit line control | Physics | 1 | Active |
| US11100964B1 | Multi-stage bit line pre-charge | Physics | 1 | Active |
| US10783954B2 | Semiconductor memory with respective power voltages for memory cells | Electricity | 1 | Active |
| US10163759B2 | Apparatus and method of three dimensional conductive lines | Electricity | 1 | Active |
| US10032490B2 | Sense amplifier layout for FinFET technology | Electricity | 1 | Active |
| US8594958B2 | Method and apparatus of electrical device characterization | Physics | 1 | Active |
| US10651114B2 | Apparatus and method of three dimensional conductive lines | Electricity | 1 | Active |
| US9799394B2 | Static random access memory (SRAM) with recovery circuit for a write operation | Physics | 0 | Active |
| US11450605B2 | Reducing internal node loading in combination circuits | Electricity | 0 | Active |
| US12300605B2 | Reducing internal node loading in combination circuits | Electricity | 0 | Active |
| US9640251B2 | Multi-port memory cell | Physics | 0 | Active |
| US12183417B2 | Memory device and manufacturing method of the same | Physics | 0 | Active |
| US11923034B2 | Header circuit placement in memory device | Electricity | 0 | Active |
| US12176026B2 | Static random access memory with a supplementary driver circuit and method of controlling the same | Physics | 0 | Active |
| US12334178B2 | Integrated circuit, system and method of forming the same | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.