Memory disturb recovery scheme for cross-point memory arrays
US10032500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Oct 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh of VLT memory bit cells that undergo a high frequency of page address read operations and write operations helps to maintain integrity of data stored in the VLT memory bit cells. The methods and systems determine, during each RAS cycle, if a rate of Page Address read operations or write operations exceeds a maximum rate across an interval, and conditionally cause a refresh operation if the rate exceeds the maximum rate. The methods and systems output a write back signal to cause a refresh of the associated VLT memory bit cells to prevent corruption of data stored in the associated VLT memory bit cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.