Embedding thin chips in polymer
US10032709B2 · kind B2 · utility
15Cited by
107References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jan 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1469
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.