Metal layer independent version identifier
US10032723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5444
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status bit, gate circuitry, first selector circuitry in a first layer, and second selector circuitry in a second layer. The gate circuitry generates a value for the status bit based at least on a first input and a second input. The first selector circuitry is coupled to the gate circuitry and is configured to select a value for the first input. The second selector circuitry is coupled to the gate circuitry and is configured to select a value for the second input. The gate circuitry generates a default value for the status bit when the first input and the second input each have a default value and generates an opposite value for the status bit when either the first input or the second input has an opposite value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.