Three-dimensional chip-to-wafer integration
US10032749B2 · kind B2 · utility
0Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.