Amit S. Kelkar
21Patents
5h-index
27Co-inventors
65Inventor score
Filing activity: Jun 1, 2000 → Sep 29, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6291367A | Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer | Electricity | 36 | Expired |
| US6489254B1 | Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG | Electricity | 15 | Expired |
| US9324687B1 | Wafer-level passive device integration | Electricity | 15 | Active |
| US9190391B2 | Three-dimensional chip-to-wafer integration | Electricity | 12 | Active |
| US9000587B1 | Wafer-level thin chip integration | Electricity | 9 | Active |
| US9704809B2 | Fan-out and heterogeneous packaging of electronic components | Electricity | 5 | Active |
| US10134689B1 | Warpage compensation metal for wafer level packaging technology | Electricity | 3 | Active |
| US6828212B2 | Method of forming shallow trench isolation structure in a semiconductor device | Electricity | 3 | Expired |
| US6824687B2 | Extraction of phenol from wastewater | Emerging Cross-Sectional Technologies | 2 | Expired |
| US9331048B2 | Bonded stacked wafers and methods of electroplating bonded stacked wafers | Electricity | 1 | Active |
| US8124916B2 | Thermal processing of silicon wafers | Electricity | 1 | Active |
| US6495475B2 | Method for fabrication of a high capacitance interpoly dielectric | Electricity | 1 | Expired |
| US8860222B2 | Techniques for wafer-level processing of QFN packages | Electricity | 1 | Active |
| US8878350B1 | Semiconductor device having a buffer material and stiffener | Electricity | 1 | Active |
| US10032749B2 | Three-dimensional chip-to-wafer integration | Electricity | 0 | Active |
| US6709990B2 | Method for fabrication of a high capacitance interpoly dielectric | Electricity | 0 | Expired |
| US8970043B2 | Bonded stacked wafers and methods of electroplating bonded stacked wafers | Electricity | 0 | Active |
| US9472451B2 | Technique for wafer-level processing of QFN packages | Electricity | 0 | Active |
| USRE40507E1 | Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG | General | 0 | Expired |
| US9040386B2 | Method for varied topographic MEMS cap process | Performing Operations; Transporting | 0 | Active |
| US9219043B2 | Wafer-level package device having high-standoff peripheral solder bumps | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.