Method for bonding pins in outer lead bonding area
US10032805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Jan 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for bonding pins in OLB area, by forming via holes on the planarization layer of the OLB area corresponding to each pin, the subsequently formed connection wires connecting the pins through the via holes above the pins so that the corresponding pins being connected by the connection wires. As the connection wires completely cover the via holes above the pins, the problem of residual conductive material in the via holes during forming the connection wires does not occur. Compared to the known technology opening a large area on the planarization layer of the OLB area, the present invention avoids the conductive material residual at the bottom of the via hole on the planarization layer and related short circuit and poor display problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.