Forming bottom isolation layer for nanosheet technology
US10032867B1 · kind B1 · utility
23Cited by
5References
10Claims
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Key dates
| Filing date | Mar 7, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Mar 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
Abstract
A method of forming a semiconductor structure includes forming a multi-layer structure. The multi-layer structure has a substrate and two or more nanosheet layers formed above the substrate. The method also includes forming a bottom isolation layer between the substrate and the two or more nanosheet layers. The method further includes performing a fin reveal in the multi-layer structure after formation of the bottom isolation layer to form a fin. The two or more nanosheet layers provide a channel stack for a nanosheet field-effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.