Method of manufacturing semiconductor devices
US10032890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Nov 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.