Data on clock lane of source synchronous links
US10033518B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 13, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Sep 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.