Nitin Gupta
64Patents
6h-index
65Co-inventors
75Inventor score
Filing activity: Jul 31, 1992 → Jul 10, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9440979B2 | Process for the preparation of pralatrexate | Chemistry; Metallurgy | 22 | Active |
| US5256964A | Tester calibration verification device | Physics | 15 | Expired |
| US8933737B1 | System and method for variable frequency clock generation | Electricity | 13 | Active |
| US10228746B1 | Dynamic distributed power control circuits | Emerging Cross-Sectional Technologies | 8 | Active |
| US9325324B1 | Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature | Electricity | 7 | Active |
| US10861508B1 | Transmitting DBI over strobe in nonvolatile memory | Physics | 7 | Active |
| US9000857B2 | Mid-band PSRR circuit for voltage controlled oscillators in phase lock loop | Electricity | 6 | Active |
| US7239176B2 | Voltage tolerant protection circuit for input buffer | Electricity | 6 | Expired |
| US11056880B1 | Snapback electrostatic discharge protection for electronic circuits | Electricity | 5 | Active |
| US9794054B2 | Data on clock lane of source synchronous links | Electricity | 3 | Active |
| US10224928B1 | On-die impedance calibration | Physics | 3 | Active |
| US10198014B2 | Low leakage low dropout regulator with high bandwidth and power supply rejection | Physics | 3 | Active |
| US10878860B1 | Multi-level signaling scheme for memory interface | Physics | 3 | Active |
| US10566980B2 | Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop | Electricity | 2 | Active |
| US10027333B2 | Phase locked loops having decoupled integral and proportional paths | Electricity | 2 | Active |
| US8786321B2 | Power harvesting in open drain transmitters | Electricity | 2 | Active |
| US10544109B2 | Process for the preparation of xylene linked cyclam compounds | Chemistry; Metallurgy | 1 | Active |
| US8314633B2 | Reducing switching noise | Electricity | 1 | Active |
| US10033518B2 | Data on clock lane of source synchronous links | Electricity | 1 | Active |
| US10838901B1 | System and method for a reconfigurable controller bridge chip | Emerging Cross-Sectional Technologies | 1 | Active |
| US11095297B2 | Phase locked loop (PLL) circuit with voltage controlled oscillator (VCO) having reduced gain | Electricity | 1 | Active |
| US8524893B2 | Process for the preparation of temsirolimus and its intermediates | Chemistry; Metallurgy | 1 | Active |
| US10862487B2 | Locked loop circuit with reference signal provided by un-trimmed oscillator | Electricity | 1 | Active |
| US8466720B2 | Frequency division of an input clock signal | Electricity | 1 | Active |
| US8183911B2 | High voltage tolerance of external pad connected MOS in power-off mode | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.