Integrated circuit device comprising environment-hardened die and less-environment-hardened die
US10036774B2 · kind B2 · utility
0Cited by
7References
19Claims
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Inventors
Key dates
| Filing date | Dec 4, 2014 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Dec 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.