Vikas Chandra
53Patents
11h-index
44Co-inventors
78Inventor score
Filing activity: Jan 19, 1999 → Nov 12, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6397359B1 | Methods, systems and computer program products for scheduled network performance testing | Electricity | 298 | Expired |
| US7342415B2 | Configurable IC with interconnect circuits that also perform storage operations | Electricity | 239 | Expired |
| US7545167B2 | Configurable IC with interconnect circuits that also perform storage operations | Electricity | 35 | Active |
| US9773550B2 | Circuit and method for configurable impedance array | Electricity | 32 | Active |
| US8488369B2 | Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device | Physics | 20 | Active |
| US10032487B2 | One-time and multi-time programming using a correlated electron switch | Physics | 18 | Active |
| US6708224B1 | Methods, systems and computer program products for coordination of operations for interrelated tasks | Physics | 17 | Expired |
| US9786370B2 | CES-based latching circuits | Electricity | 17 | Active |
| US7093251B2 | Methods, systems and computer program products for monitoring interrelated tasks executing on a computer using queues | Physics | 14 | Expired |
| US8161367B2 | Correction of single event upset error within sequential storage circuitry of an integrated circuit | Physics | 12 | Active |
| US6948017B2 | Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus | Physics | 11 | Expired |
| US8363484B2 | Memory device and method of controlling a write operation within a memory device | Physics | 11 | Active |
| US8164964B2 | Boosting voltage levels applied to an access control line when accessing storage cells in a memory | Physics | 11 | Active |
| US8339876B2 | Memory with improved read stability | Physics | 10 | Active |
| US8171386B2 | Single event upset error detection within sequential storage circuitry of an integrated circuit | Physics | 9 | Active |
| US8493120B2 | Storage circuitry and method with increased resilience to single event upsets | Physics | 8 | Active |
| US9483664B2 | Address dependent data encryption | Electricity | 7 | Active |
| USD792090S1 | Multipurpose bag | General | 7 | Active |
| US8285767B2 | Apparatus and method for generating a random number | Physics | 7 | Active |
| US8407540B2 | Low overhead circuit and method for predicting timing errors | Physics | 5 | Active |
| US9891976B2 | Error detection circuitry for use with memory | Physics | 5 | Active |
| US9870306B2 | Exception prediction before an actual exception during debugging | Physics | 3 | Active |
| US9529671B2 | Error detection in stored data values | Physics | 2 | Active |
| US10922608B2 | Spiking neural network | Physics | 2 | Active |
| US7793181B2 | Sequential storage circuitry for an integrated circuit | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.