Transformation on input operands to reduce hardware overhead for implementing addition
US10037190B2 · kind B2 · utility
0Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | May 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.