Inventor · Peekskill, NY, US

Ruchir Puri

73Patents
12h-index
106Co-inventors
87Inventor score

Filing activity: Jun 6, 1994 → Jun 30, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US11068797B2 Automatic correction of indirect bias in machine learning models Physics 110 Active
US5469367A Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits Physics 73 Expired
US8839162B2 Specifying circuit level connectivity during circuit design synthesis Physics 58 Active
US8271920B2 Converged large block and structured synthesis for high performance microprocessor designs Physics 29 Active
US7225421B2 Clock tree distribution generation by determining allowed placement regions for clocked elements Physics 24 Expired
US7521950B2 Wafer level I/O test and repair enabled by I/O layer Physics 16 Active
US7913202B2 Wafer level I/O test, repair and/or customization enabled by I/O layer Physics 16 Active
US7119578B2 Single supply level converter Electricity 14 Expired
US7448014B2 Design stage mitigation of interconnect variability Emerging Cross-Sectional Technologies 14 Expired
US7111266B2 Multiple voltage integrated circuit and design method therefor Physics 13 Expired
US8104014B2 Regular local clock buffer placement and latch clustering by iterative optimization Physics 13 Active
US8495552B1 Structured latch and local-clock-buffer planning Physics 13 Active
US8010926B2 Clock power minimization with regular physical placement of clock repeater components Physics 11 Active
US6724225B2 Logic circuit for true and complement signal generator Electricity 9 Expired
US9824756B2 Mapping a lookup table to prefabricated TCAMS Physics 9 Active
US6601223B1 System and method for fast interconnect delay estimation through iterative refinement Physics 8 Expired
US8261226B1 Network flow based module bottom surface metal pin assignment Physics 8 Active
US8527920B1 Automated synthesis of high-performance two operand binary parallel prefix adder Physics 7 Active
US6018621A Identifying an optimizable logic region in a logic network Physics 7 Expired
US9606934B2 Matrix ordering for cache efficiency in performing large sparse matrix operations Physics 7 Active
US5903467A Selecting phase assignments for candidate nodes in a logic network Physics 7 Expired
US7089510B2 Method and program product of level converter optimization Physics 7 Expired
US8516412B2 Soft hierarchy-based physical synthesis for large-scale, high-performance circuits Physics 6 Active
US6958545B2 Method for reducing wiring congestion in a VLSI chip design Physics 6 Expired
US7480883B2 Multiple voltage integrated circuit and design method therefor Physics 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.