Operation of a multi-slice processor with an expanded merge fetching queue
US10037211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where each load/store slice includes a load miss queue and a load reorder queue, includes: receiving, at a load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; and if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.