Inventor · Oronoco, MN, US

Elizabeth A. McGlone

45Patents
6h-index
27Co-inventors
65Inventor score

Filing activity: Jun 3, 2004 → Jun 8, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US7984357B2 Implementing minimized latency and maximized reliability when data traverses multiple buses Physics 17 Active
US7882323B2 Scheduling of background scrub commands to reduce high workload memory request latency Physics 14 Active
US10037211B2 Operation of a multi-slice processor with an expanded merge fetching queue Physics 12 Active
US7328315B2 System and method for managing mirrored memory transactions and error recovery Physics 11 Expired
US9043526B2 Versatile lane configuration using a PCIe PIe-8 interface Physics 9 Active
US9983875B2 Operation of a multi-slice processor preventing early dependent instruction wakeup Physics 8 Active
US8949499B2 Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch Physics 6 Active
US10042647B2 Managing a divided load reorder queue Physics 6 Active
US10037229B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 6 Active
US10042770B2 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Physics 6 Active
US7882314B2 Efficient scheduling of background scrub commands Physics 6 Active
US9292460B2 Versatile lane configuration using a PCIe PIE-8 interface Physics 4 Active
US8266331B2 Transmitting retry request associated with non-posted command via response credit channel Physics 4 Active
US7761669B2 Memory controller granular read queue dynamic optimization of command selection Physics 4 Active
US8397100B2 Managing memory refreshes Physics 3 Active
US8572455B2 Systems and methods to respond to error detection Physics 3 Active
US9684618B2 Peripheral component interconnect express (PCIe) ping in a switch-based environment Emerging Cross-Sectional Technologies 3 Active
US8103930B2 Apparatus for implementing processor bus speculative data completion Physics 3 Active
US8132048B2 Systems and methods to efficiently schedule commands at a memory controller Physics 2 Active
US9563591B2 Peripheral component interconnect express (PCIe) ping in a switch-based environment Emerging Cross-Sectional Technologies 2 Active
US7472236B2 Managing mirrored memory transactions and error recovery Physics 2 Active
US7516270B2 Memory controller and method for scrubbing memory without using explicit atomic operations Physics 2 Active
US9292462B2 Broadcast for a distributed switch network Physics 2 Active
US8898359B2 Bandwidth limiting on generated PCIe packets from debug source Physics 2 Active
US8539309B2 System and method for responding to error detection Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.