Dual-port memories and input/output circuits for preventing failures corresponding to concurrent accesses of dual-port memory cells
US10037290B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.