Peter Wung Lee
191Patents
32h-index
28Co-inventors
90Inventor score
Filing activity: Feb 8, 1984 → Apr 29, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7164608B2 | NVRAM memory cell architecture that integrates conventional SRAM and flash cells | Physics | 346 | Expired |
| US5768193A | Bit-refreshable method and circuit for refreshing a nonvolatile flash memory | Physics | 138 | Expired |
| US5748538A | OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array | Physics | 130 | Expired |
| US5953255A | Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance | Physics | 126 | Expired |
| US5822252A | Flash memory wordline decoder with overerase repair | Physics | 122 | Expired |
| US5978283A | Charge pump circuits | Electricity | 117 | Expired |
| US6381670B1 | Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation | Physics | 103 | Expired |
| US6714457B1 | Parallel channel programming scheme for MLC flash memory | Physics | 88 | Expired |
| US6031765A | Reversed split-gate cell array | Physics | 74 | Expired |
| US5748545A | Memory device with on-chip manufacturing and memory cell defect detection capability | Physics | 65 | Expired |
| US5835420A | Node-precise voltage regulation for a MOS memory system | Physics | 63 | Expired |
| US6620682B1 | Set of three level concurrent word line bias conditions for a nor type flash memory array | Electricity | 61 | Expired |
| US6556481B1 | 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell | Physics | 60 | Expired |
| US6862223B1 | MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT | Physics | 59 | Expired |
| US8120959B2 | NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same | Physics | 55 | Active |
| US6023188A | Positive/negative high voltage charge pump system | Electricity | 50 | Expired |
| US5777923A | Flash memory read/write controller | Physics | 47 | Expired |
| US6498752B1 | Three step write process used for a nonvolatile NOR type EEPROM memory | Physics | 46 | Expired |
| US7369438B2 | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications | Electricity | 46 | Expired |
| US5930826A | Flash memory protection attribute status bits held in a flash memory array | Physics | 45 | Expired |
| US6757196B1 | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device | Electricity | 43 | Expired |
| US6009022A | Node-precise voltage regulation for a MOS memory system | Physics | 43 | Expired |
| US6850438B2 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Physics | 40 | Expired |
| US5920503A | Flash memory with novel bitline decoder and sourceline latch | Physics | 40 | Expired |
| US5774396A | Flash memory with row redundancy | Physics | 40 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.