Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method
US10037293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2016 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Sep 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.