Patent · US Active

Hierarchical timing analysis for multi-instance blocks

US10037394B1 · kind B1 · utility

8Cited by

1References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Pawan Kulshreshtha · San Jose, US
Amit Dhuria · Sidhauli, IN

Key dates

Filing date	Jun 14, 2016
Grant date	Jul 31, 2018
Priority date	—
Expiry date	Jun 14, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.