Amit Dhuria
11Patents
5h-index
16Co-inventors
55Inventor score
Filing activity: Mar 15, 2013 → Jun 30, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8788995B1 | System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design | Physics | 43 | Active |
| US8863052B1 | System and method for generating and using a structurally aware timing model for representative operation of a circuit design | Physics | 36 | Active |
| US10037394B1 | Hierarchical timing analysis for multi-instance blocks | Physics | 8 | Active |
| US9405882B1 | High performance static timing analysis system and method for input/output interfaces | Physics | 5 | Active |
| US10169501B1 | Timing context generation with multi-instance blocks for hierarchical analysis | Physics | 5 | Active |
| US10990733B1 | Shared timing graph propagation for multi-mode multi-corner static timing analysis | Physics | 5 | Active |
| US9529962B1 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Physics | 4 | Active |
| US11003821B1 | Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits | Physics | 3 | Active |
| US10133842B1 | Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs | Physics | 3 | Active |
| US11144698B1 | Method, system, and product for an improved approach to placement and optimization in a physical design flow | Physics | 1 | Active |
| US11188696B1 | Method, system, and product for deferred merge based method for graph based analysis pessimism reduction | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.