Patent · US Active

SRAM read multiplexer including replica transistors

US10037794B1 · kind B1 · utility

0Cited by

2References

17Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Dhori Kedar Janardan · Mahesana, IN
Abhishek Pathak · Kathiatoli, IN
Shishir Kumar · Greater Noida, IN

Key dates

Filing date	Jul 26, 2017
Grant date	Jul 31, 2018
Priority date	—
Expiry date	Jul 26, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.