Inventor · Greater Noida, IN

Shishir Kumar

33Patents
3h-index
24Co-inventors
59Inventor score

Filing activity: Dec 28, 2006 → Mar 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9006841B2 Dual port SRAM having reduced cell size and rectangular shape Electricity 36 Active
US7545180B2 Sense amplifier providing low capacitance with reduced resolution time Physics 7 Active
US10283191B1 Method and circuit for adaptive read-write operation in self-timed memory Physics 4 Active
US10998077B2 Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory Physics 2 Active
US10191902B2 Method and unit for building semantic rule for a semantic data Physics 2 Active
US11532633B2 Dual port memory cell with improved access resistance Electricity 1 Active
US9165642B2 Low voltage dual supply memory cell with two word lines and activation circuitry Physics 1 Active
US11152376B2 Dual port memory cell with improved access resistance Electricity 1 Active
US11742045B2 Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory Physics 1 Active
US10073838B2 Method and system for enabling verifiable semantic rule building for semantic data Physics 1 Active
US12272424B2 Reducing spurious write operations in a memory device Physics 0 Active
US12112818B2 Scan chain compression for testing memory of a system on a chip Physics 0 Active
US12353717B2 Localized and relocatable software placement and NoC-based access to memory controllers Physics 0 Active
US11889675B2 Dual port memory cell with improved access resistance Electricity 0 Active
US11025252B2 Circuit for detection of single bit upsets in generation of internal clock for memory Electricity 0 Active
US12340864B2 Interface level-shifter dual-rail memory architecture Physics 0 Active
US9147453B2 Programmable delay introducing circuit in self timed memory Physics 0 Active
US8138455B2 Programmable delay introducing circuit in self timed memory Physics 0 Active
US12019908B2 Dynamically allocated buffer pooling Physics 0 Active
US10706915B2 Method and circuit for adaptive read-write operation in self-timed memory Physics 0 Active
US11521697B2 Circuit and method for at speed detection of a word line fault condition in a memory circuit Physics 0 Active
US8963053B2 Programmable delay introducing circuit in self-timed memory Physics 0 Active
US11195576B2 Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier Physics 0 Active
US12316326B1 Delay circuit Electricity 0 Active
US12094513B2 Power supply tracking circuitry for embedded memories Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.