Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation
US10037810B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jun 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.