Semiconductor memory device
US10037813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least four threshold voltages, a first bit line, a word line, and a first sense amplifier which is connected to the first bit line. The first sense amplifier applies a charging voltage to the first bit line in a first verification operation in which a first voltage is applied to the word line, does not apply the charging voltage to the first bit line in a second verification operation in which a second voltage higher than the first voltage is applied to the word line, and applies the charging voltage to the first bit line BL in a third verification operation in which a third voltage higher than the second voltage is applied to the word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.