Memory controller, memory system including the same and operating method thereof
US10037816B2 · kind B2 · utility
1Cited by
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18Claims
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Key dates
| Filing date | Jul 12, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller may include a detector configured for checking whether the number of bits having a first state among a plurality of bits constituting write data is less than a reference value. The memory controller may include an inverter configured for inverting/non-inverting the write data according to the check result of the detector. The detector may generate an error detection signal based on whether or not the number of bits having the first state among a plurality of bits constituting read data is equal to or more than the reference value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.