Methods and apparatuses for optimizing power and functionality in transistors

US10037992B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Zhiyuan Wu · Shanghai, CN
• Ning Cheng · San Jose, US
• Christopher J. Pass · San Jose, US

Key dates

• Filing date: Dec 22, 2014
• Grant date: Jul 31, 2018
• Expiry date: Aug 11, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A transistor device is provided. The transistor device includes a group of fins formed in a substrate, where the group of fins comprises at least one enabled fin and at least one disabled fin. Each of the fins has first and second fin portions. The first fin portion encompasses a drain region and the second fin portion of the fins encompasses a source region. These two regions are separated by a channel region. A gate structure is formed over the fins and channel region and in between the first fin portion and the second fin portion of the fins. The transistor device further includes a conductive structure. The conductive structure shorts the first fin portion of the at least one disabled fin to the second fin portion of the at least one disabled fin.