Memory cell and non-volatile semiconductor storage device
US10038101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2015 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Oct 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.