Low insertion loss package pin structure and method
US10038259B2 · kind B2 · utility
0Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2014 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.