Device for correcting multi-phase clock signal
US10038433B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.